This invention relates to a semi-custom semiconductor device adapted for a master slice approach such as a gate array and embedded cell array and a method for fabricating the same. More particularly, it relates to a semiconductor device capable of sharing a mask for forming connection holes in steps of forming custom wiring for fabricating a semi-custom semiconductor device adapted for a master slice approach to form a desired logic, and a method for fabricating the semiconductor device which method can reduce the number of the steps of forming the custom wiring and shorten the period taken until product delivery.
In semiconductor devices such as IC and LSI, a variety of elements are formed on a semiconductor substrate and electrically interconnected by applying wiring lines between the elements. The recent advance in integration and miniaturization of elements requires to use a multi-level wiring structure of two or more layers for interconnection. Then in semiconductor devices, for example, semi-custom semiconductor devices intended for a master slice approach such as gate arrays, elements formed on a semiconductor substrate are electrically connected by way of through-holes. In the case of a gate array, for example, a diffusion layer and a gate constituting a basic cell and a first wiring layer are electrically connected through contact holes, and wiring layers, for example, first and second wiring layers are electrically connected through via holes.
In the fabrication of a gate array, a common master wafer is prepared using a common diffusion mask and insulating mask which are previously designed and fabricated. A specific metal wiring layer-forming mask corresponding to a logic circuit design is designed and prepared. By using such a mask in the final step of processing the semiconductor wafer, a circuit design term is shortened. To facilitate the designing of a gate array, that is, to facilitate the designing of a specific metal wiring layer (custom wiring layer) corresponding to a circuit design, JP-A 28786/1975 discloses to form a custom wiring layer by using a grid structure having a uniform lattice spacing, thereby facilitating the designing of a semiconductor device by means of a computer.
FIG. 7 illustrates the structure of a wiring grid having a uniform lattice spacing relative to basic cells in a prior art gate array. A basic cell 102 includes a diffusion layer 104 consisting of a P type (p.sup.+) diffusion layer 104a and a N type (n.sup.+) diffusion layer 104b and two gate electrodes 106 formed on each of the diffusion layers 104a and 104b through a gate oxide film. A plurality of such basic cells 102 are arranged in a grid array on a master chip 108 on which are distributed a wiring grid 110 having a uniform spacing and lattice points 112 of a connection hole (contact hole or via hole) placeable position-defining grid which are coincident with lattice points or intersections of the wiring grid 110. That is, the connection hole placeable position-defining grid (112) and the wiring grid 110 are coincident with each other or coincident with each other at least in one direction, with the lattice points 112 or points on the wiring grid 110 between adjacent lattice points 112 presenting connection hole placeable positions. Therefore, the prior art gate array has such a structure that contact hole placeable positions (112) of the basic cell 102 and via hole placeable positions (112) between wiring layers are present on the customizing wiring grid 110 as in the illustrated example.
FIG. 8(a) illustrates an example in which metal wirings 114 and 116 are applied to a basic cell 102 in a gate array of such a structure. The diffusion layer 104 and a first layer metal wiring 114 formed on the wiring grid 110 are electrically connected through a contact hole 118 perforated at a lattice point 112 of the wiring grid 110 which is a contact hole placeable position. The first layer metal wiring 114 and a second layer metal wiring 116 formed on the wiring grid 110 are electrically connected through a via hole 120 formed (at an intermediate) between adjacent lattice points 112 on the wiring grid 110 which is a via hole (connection hole) placeable position. It is understood that in FIG. 8(a), first and second insulating layers 122 and 124 are omitted for brevity's sake.
FIGS. 8(b) and 8(c) are an enlarged plan view and a cross-sectional view of a portion around the contact hole 118. In these figures, the second insulating layer 124 is omitted for brevity's sake. The contact hole 118 is formed at the position of a lattice point 112 by perforating the first insulating layer 122 deposited on the diffusion layer 104 through a contact hole-forming special mask. The thus formed contact hole 118 is filled with a metal forming the first layer metal wiring, for example, aluminum (Al) during formation of the first layer metal wiring using a first layer metal wiring-forming mask, with the resulting metal fill 115 electrically connecting the diffusion layer 104 and the first layer metal wiring 114. At this point, a wiring connection 114a is formed above the contact hole 118 which is of a rectangular shape having a greater size than the line width of the first layer metal wiring 114 and spreads over the first insulating layer 122, ensuring the above-mentioned electrical connection.
FIGS. 8(d) and 8(e) are an enlarged plan view and a cross-sectional view of a portion around the via hole 120. The via hole 120 is formed at approximately an intermediate between adjacent lattice points 112 on the wiring grid 110 by perforating the second insulating layer 124 deposited on the wiring connection 114a of the first layer metal wiring 114 on the first insulating layer 122 through a via hole-forming special mask. The thus formed via hole 120 is filled with a metal forming the second layer metal wiring 116, for example, aluminum (Al), with the resulting metal fill 117 electrically connecting the first and second layer metal wirings 114 and 116.
The wiring grid 110 has a lattice spacing L sufficient to prevent two wiring connections 114a associated with contact holes 118 from contacting with each other during fabrication even when the wiring connections 114a are adjacent to each other. As shown in FIG. 9, the lattice spacing L is given as a sum of the minimum distance a between the opposed edges of the two wiring connections 114a and the width W of the wiring connection 114a, that is, a+W.
FIG. 10 schematically illustrates the structure of such a prior art semi-custom semiconductor using a master slice approach, for example, a master wafer of a gate array and a double metal wiring process during fabrication of a semiconductor device using the master wafer.
FIG. 10(a) illustrates a master wafer 100 of a CMOS (complementary metal-oxide semiconductor) conventional gate array. The master wafer 100 includes a basic cell 102 which has P.sup.+ diffusion layers 104a formed in a N type silicon (Si--N) substrate 101 and a P well 103 also formed therein in which n.sup.+ diffusion layers 104b are formed. An element isolation film 107 of SiO.sub.2 is formed between the diffusion layers 104a and 104b by local oxidation of silicon (LOCOS). A polysilicon gate 106 is formed above and between two P.sup.+ diffusion layers 104a through a gate oxide film 105. A first interlayer insulating film (e.g., a PSG film) 122 covers the entire surface of underlying element layers of the basic cell 102.
FIGS. 10(b) to 10(g) illustrate successive customizing steps for fabricating a semi-custom semiconductor device by applying double metallizations to the master wafer 100 coated with the first interlayer insulating film 122 over the entire surface thereof.
First referring to FIG. 10(b), only contact holes 118 for providing contacts are perforated in the first interlayer insulating film 122 of the master wafer 100 by etching through a contact hole-forming custom mask or reticle. Then as shown in FIG. 10(c), a first metal layer 114 is formed which fills the contact holes 118 and covers the entire surface of the first interlayer insulating film 122. Then as shown in FIG. 10(d), the first metal layer 114 is etched through a customizing first layer wiring-forming mask or reticle to form a first layer metal wiring 114 having a predetermined custom wiring pattern. Then as shown in FIG. 10(e), a second interlayer insulating film 124 is deposited thereon which covers the entire surface.
Thereafter, as shown in FIG. 10(f), only via holes 120 for use in interconnection between metal wiring layers are perforated in the second interlayer insulating film 124 by etching through a via hole-forming custom mask or reticle. Then as shown in FIG. 10(g), a second metal layer 116 is formed which fills the via holes 120 and covers the entire surface of the second interlayer insulating film 124. Then though not shown, but as in FIG. 10(d), the second metal layer 116 is etched through a customizing second layer wiring-forming mask or reticle to form a second layer metal wiring 116 having a predetermined custom wiring pattern. Then though not shown, a passivation film is formed on the second layer metal wiring 116, the passivation film is etched through a common passivation via mask to form bonding via holes, and bonding pads are formed before a semiconductor device is completed.
As mentioned above, interconnections between an underlying element layer and a metal wiring layer and between metal wiring layers in the conventional gate array are generally provided through contact holes and via holes. Cost reducing approaches upon development of such a gate array include sharing of underlying masks for forming underlying layers of the basic cell and sharing of passivation via masks for forming bonding pads, whereby a cost reduction is accomplished by reducing the number of masks or reticles formed upon development.
Also the old-fasioned gate array has a structure wherein in a core of a master chip forming a basic cell, a plurality of element or cell-forming regions in each of which a plurality of basic cells are arranged in a row are arranged with wiring or channel regions being interposed therebetween, and cell-to-cell interconnections are formed in the wiring regions. However, for higher integration, sea-of-gates (SOG) type gate arrays or channelless gate arrays having no special wiring region in the core is recently employed for achieving improvements in the degree of integration of gates per chip area and in the flexibility of placement and wiring. High integration gate arrays employ a combination of various techniques as mentioned above.
Moreover, with respect to the channel gate array, for a cost reduction upon development, JP-A 46048/1985 discloses a technique for reducing the number of masks or reticles to be formed upon development by sharing a via hole-forming mask in a wiring region. This technique intends to share a via hole-forming mask by providing connection between an upper wiring layer and a lower wiring layer sandwiching an interlayer insulating film through a via hole which is formed at a position overlapping one wiring layer, but not overlapping the other wiring layer.
The prior art gate array disclosed in JP-A 28786/1975 referred to above and shown in FIGS. 7, 8 and 9 cannot share contact holes or via holes because the metal wiring pattern to be designed for each wiring layer is different for each of circuits. Whenever the circuit design is altered, a set of a contact hole-forming mask as well as a metal wiring-forming mask and a set of a via hole-forming mask and a metal wiring-forming mask, four special masks in total, must be newly prepared, failing to reduce the mask forming cost, to reduce the mask forming time frame, and to advance the product delivery date. Furthermore, whenever one layer of metal wiring is added, two masks of the via hole-forming mask and the metal wiring-forming mask have to be prepared, which causes an increase in production cost. Especially prior art high integration sea-of-gates type gate arrays need to customize a contact hole-forming mask and respective via hole-forming masks (excluding a passivation via hole-forming mask), resulting in a substantially increased development cost.
In the channel gate array disclosed in JP-A 46048/1985, since upper and lower wirings and via holes are formed in special wiring regions, a via hole-forming mask can be shared. However, since the wiring of either the upper or lower wiring layer cannot be equally spaced, a wiring grid having a uniform lattice spacing cannot be used. This undesirably prevents easy computer-aided designing of semiconductor integrated circuits. Further, since the high integration sea-of-gates type (channelless) gate array is free of a special wiring region, a contact hole-forming region and a via hole-forming region overlap, rendering it impossible to share a via mask. The channel gate array wiring technique disclosed in this publication is not applicable to a channelless gate array.
Among the prior art wiring techniques including the one disclosed in JP-A 46048/1985, there is not an available technique of sharing a contact hole-forming mask for providing interconnection between an underlying layer and a wiring layer. Further, since a master wafer for a conventional semi-custom semiconductor device such as a gate array has completed the step of forming the first interlayer insulating film as shown in FIG. 10(a), the double metal wiring process requires four customized masks as mentioned above, failing to shorten the customizing step and to advance the product delivery date.